1. Field
Some example embodiments of the inventive concepts may relate generally to memory controllers. Some example embodiments of the inventive concepts may relate generally to memory systems including such memory controllers. Some example embodiments of the inventive concepts may relate generally to memory controllers supporting self-encryption. Some example embodiments of the inventive concepts may relate generally to operating methods of memory controllers. Some example embodiments of the inventive concepts may relate generally to memory systems including such memory controllers.
2. Description of Related Art
The term “non-volatile memory” may refer to kinds of memory capable of retaining stored data even if a power supply is shut off. In recent years, data storages including high-capacity non-volatile memories may be widely employed and may be usefully adopted to store or transfer large amounts of data.
As capacities of data storages have gradually increased and as the portability of the data storages has improved, there may be growing likelihood that the data storages will be misused as units for secretly transferring vast amounts of data. In particular, manufacturers, state organizations, and financial institutions using information that needs security may require measures for preventing the information from being taken out by using the data storages.
In some example embodiments, a three-dimensional (3D) memory array may be provided. The 3D memory array may be monolithically formed in one or more physical levels of arrays of memory cells having an active area above a silicon substrate, and circuitry associated with the operation of those memory cells, whether such associated circuitry is above or within such substrate. The term “monolithic” means that layers of each level of the array may be directly deposited on the layers of each underlying level of the array.
In some example embodiments, the 3D memory array may include vertical NAND (VNAND) strings that are vertically oriented such that at least one memory cell is located over another memory cell. The at least one memory cell may comprise a charge trap layer.
The following patent documents, the entire contents of which are incorporated herein by reference, describe suitable configurations for three-dimensional memory arrays, in which the three-dimensional memory array may be configured as a plurality of levels, with word lines and/or bit lines shared between levels: U.S. Pat. No. 7,679,133 B2; U.S. Pat. No. 8,553,466 B2; U.S. Pat. No. 8,559,235 B2; U.S. Pat. No. 8,654,587 B2; and U.S. Patent Publication No. 2011/0233648 A1.